1) Field of the Invention
This invention relates generally to methods for the electrical measurement of critical dimensions and more particularly to electrical measurement of line spacing of conductive structures in semiconductor devices.
2) Description of the Prior Art
An important driver for keeping Moore's Law is the improvement in productivity of semiconductor manufacturing. This is accomplished by the constant shrinking of device structures. The main burden of this shrink roadmap is carried by the lithography, which is currently pushed to its physical limits. The lithography process and exposure tools require an ever growing effort and support from metrology and inspection. New procedures are needed here to guarantee the required precision and accuracy specifications as well as the requirements for throughput and statistical significance.
The low-voltage scanning electron microscope (SEM) is a main metrology tool for critical dimension (CD) monitoring. Typically, the time required for CD-SEM measurement limits the number of measurement sites to be collected per wafer. However, some applications require a metrology tool, which is able to collect large amounts of data within a short time frame to obtain statistically significant results on the complete image fields. One example is the characterization of lithographic exposure tools based on an assessment of their actual printing performance by measurement of line spacing.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
Jason P. Cain and Costas J. Spanos, Electrical linewidth metrology for systematic CD variation characterization and casual analysis, found Jul. 18, 2005 on website, 12 pages, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, Calif. 94720
U.S. Pat. No. 6,573,498: Electric measurement of reference sample in a CD-SEM and method for calibration—Scanning electron microscope calibrating method for semiconductor device manufacture, involves correlating optical workpiece measurement with reference sample feature critical dimension Inventor: Rangarajan, Bharath; et al.
US20030155933A1: Dielectric test structure and test method—Dielectric layer test structure for semiconductor device manufacture, has line pads and conductive layers formed inside dielectric layer—Inventor: Wang, Mu-Chun
U.S. Pat. No. 6,754,593: Method and apparatus for measuring defects—Workpiece e.g. microprocessor defect measuring method, involves measuring defect characteristics at each of measurement sites on workpiece responsive to measured defect characteristics being greater than predetermined threshold Inventor: Stewart, Edward C.; Buda, Tex.
U.S. Pat. No. 6,891,627: Methods and systems for determining a critical dimension and overlay of a specimen—Specimen properties determining system for semiconductor fabrication process, determines critical dimension and overlay misregistration of specimen based on output signals generated by measurement device Inventor: Levy, Ady
U.S. Pat. No. 6,242,757: Capacitor circuit structure for determining overlay error—Error determination structure for integrated circuit manufacture, has pairs of contact areas which oppose sides of square, so that capacitor areas are extended inwards and overlapping sides of square—Inventor: Tzeng, Kuo-Chyuan
US20020107650A1: Methods and systems for determining a critical dimension and a presence of defects on a specimen—Specimen properties determining system for semiconductor fabrication process, determines critical dimension and overlay misregistration of specimen based on output signals generated by measurement device Inventor: Wack, Dan; et al.
US20020102472A1: Electrical critical dimension measurements on photomasks—Test structure for measuring critical distances on photomasks, includes cross-resistor, bridge resistor and split-bridge structures connected to image line, for performing sheet resistance and other measurements—Inventor: Chan, David Y.; Austin, Tex., United